Solved: K20 UART with 2 stop bit or parity

Hi Massimiliano

If you configure for 1 stop bit (which you have to) it won't have any implecations for your receiver - should the peer be configured for 2 stop bits you will already completely receive each character after 1 stop bit and the second will simply be an additional 1 bit period pause (IDLE),

The peer could however have problems when configured for 2 stop bits and you send only 1. This can happen when you send two characters "immediately" after another and the start bit of the second character is sent after just 1 stop bit time, while the peer is still waiting for the second stop bit to arrive. In the worst case the peer's receiver will see your start bit as an invalid second stop bit and then also miss the start bit and hence the next character will be corrupted. However the peer, while working in 2 stop bit mode may also simply accept that there was a fast new start bit and so not have any problems. Therefore what actually happens is undefined.

To avoid the potential problem the only option is to insert a slight pause between each transmitted character or at least 1 bit time. DMA transmission is not possible becaue it will send multiple bytes without any pauses, but when interrupt driven the "transmit complete flag" interrupt can be used instead of the "transmit buffer empty" interrupt. The interesting thing about this interrupt is that is that immediately writing the next character when it occurs inserts a single bit idle period onto the UART Tx, which is in fact exactly what you need. The reason for this is that the UART works with a bit clock equal to the BAUD rate (rather than being purely asynchronous) and exactly when the "transmit complete flag" interrupt fires the next bit is clocked out - since there is no data byte in the DATA register at that instance an idle bit is inserted. At the next bit time you will probably have already written the next Tx byte into the DATA register and so the UART will then insert the start bit of the next character.

This timing is probably conincidence but it does in fact allow true 2 stop bit transmission to be realised with an interrupt driven UART driver.

>>How to use Parity with 8 data bits?

For 7 bit mode with parity write UART_C1 with PE and optionally PT (7 bit even or odd parity)

For 8 bit mode with parity write UART_C1 with M and PE and optionally PT (8 bit even or odd parity)

Therefore use the M bit to control the data length you want

Regards

Mark

P.S. Strangely, the UARTs 1 and higher in the KL parts do support 2 stop bit mode, as does the LPUART in the KL03.

http://www.utasker.com/kinetis.html

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