Hi,

Thak you very much for your response and for pointing this mistake out to me.  I've made some progress now.  I have the reference design loaded onto the FPGA and now and it's running.  I'm having some trouble understanding the output signals though. Note, I only care about the transmission path, i.e., the DACs.

I have the IIO Oscilloscope running with the AD9081 plugin, and the connection is working.   It seems that I'm missing perhaps some explanation or block diagram of how the AD9081 is configured in terms of its FDUC and CDUC as part of this particular reference design.  I'm following the link:

AD9081-FMCA-EBZ / AD9082-FMCA-EBZ (Single MxFE) HDL Reference Design [Analog Devices Wiki]

and in this link I only see the block diagrams of what I understand are the parts up to the FMC connector.  So for example, for the M4, L8, it seems that I have a sample data output of 250MHz.  I know also that the DAC frequency is 12 GHz (it says so on the AD9081 plugin).  So my first set of questions are:

1. How is the data channeled and up converted inside the AD9081 in this reference design?  Currently I can get output signals to change but can't figure out why they're at those frequencies. 

2. Please see the attached figure.  In the TX chain, it says for Channel 1: [FDUC0->CDUC3->DAC3],  and for Channel 2: [FDUC1->CDUC3->DAC3]

  a. How can they both be routed to DAC3?

  b.  I'm actually only getting a signal out of DAC0 and DAC1 for TX1 and TX2 respectively.  What is going on?