Thanks Filip for your reply. My question though is not about it. In AD9082 FMCA EBZ evaluation board, it's possible to feed the AD9082 chip with external clock and sysref. But according to the clocking block diagram (figure 14), these external clocks don't go to the FMC connector to feed the FPGA as well. Therefore, we have to use the other FPGA MGT clocks (out of the FMC) to get the external clock. Normally the data and clock ports of a JESD IP core should be taken from the same FPGA bank. While in this case it's not possible. I'm just wondering if the JESD IP core in the AD9082 HDL ref design is sensitive to the bank that JESD data and clock have been taken from (they must be from the same FPGA bank)?
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