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AMD Ryzen Threadripper Pro 3955WX Review the Lower

#AMD Ryzen Threadripper Pro 3955WX Review the Lower| 来源: 网络整理| 查看: 265

AMD Threadripper Pro 3955WX CoverAMD Threadripper Pro 3955WX Cover

The AMD Threadripper Pro series we have dubbed the “WEPYC” because it is effectively a workstation EPYC. While we previously reviewed the聽AMD Ryzen Threadripper PRO 3995WX we wanted to take a look at the other end of the spectrum, the lower-end 16-core model. With the AMD Threadripper Pro 3955WX, we have a 16-core option that is one-quarter the core count of the top-end units so we wanted to see whether this is worth it. What we found, and our suspicion is that this part has a very specific place in the overall line-up.

AMD Ryzen Threadripper Pro 3955WX Overview

The AMD Threadripper Pro 3955WX is a 16-core part, but it is really designed to be something different in the series. In our overview, we wanted to focus on two major themes for this chip. First, the chips specs and layout. Second, we wanted to focus on the platform aspects.

Key stats for the AMD Threadripper Pro 3955WX: 16 cores / 32 threads with a 3.9GHz base clock and 4.3GHz turbo boost. There is 64MB of onboard L3 cache. The CPU features a 280W TDP. These are $1099 list price parts.

Here is the lscpu output for the Threadripper Pro 3955WX:

AMD Threadripper Pro 3955WX Lscpu OutputAMD Threadripper Pro 3955WX Lscpu Output

One of the more interesting aspects of this CPU is the topology. With 16 cores only 64MB of onboard L3 cache, it seems significantly different than the 3975WX (32 core) and 3995WX (64 core.) Indeed this is a 4MB/ core part like the 3995WX, however, that presents a challenge with the layout. AMD EPYC (and Threadripper Pro) CPUs effectively have an I/O die that handles the PCIe and memory controllers, and then up to eight x86 compute dies surrounding the I/O die.

AMD EPYC Rome 1P PCIe In RedAMD EPYC Rome 1P PCIe In Red

Since the Threadripper Pro line is effectively a high-TDP EPYC with a chipset for the workstation market, we wanted to see what the layout of the chip is. Here is the topology output for the chip (with the PCIe information pulled out since that took up a lot of screen space in this system):

AMD Threadripper Pro 3955WX TopologyAMD Threadripper Pro 3955WX Topology

What we can see here is that the 3955WX has four cores sharing 16MB L3 cache segments. Four of those give us 16 cores and 64MB of L3 cache. This looks fairly similar to the聽AMD EPYC 7282 configuration:

AMD EPYC 7282 Topology ExampleAMD EPYC 7282 Topology Example

It is also not the only configuration AMD has for a 16-core Zen2 CPU. Here is an example from our AMD EPYC 7F52 review where you can see a significantly different layout.

AMD EPYC 7F52 TopologyAMD EPYC 7F52 Topology

The EPYC 7F52 has 16 cores and each core has 16MB of L3 cache for 256MB total. You can clearly see the difference between the frequency optimized 16-core EPYC 7002 part and this Threadripper Pro 3955WX frequency optimized 16-core workstation part.

This layout distinction is important. AMD’s architecture uses large L3 caches to help performance. While, in theory, AMD can get higher clock speeds with fewer compute die packages to cool, AMD’s architecture tends to do much better with the high core to cache ratios. That is why the EPYC 7282 is more like 1/8th or so of the cost of the EPYC 7F52.

With this background, AMD had to build a 16-core Threadripper Pro part with a $1099 target price. If the company had built this chip in the configuration of the EPYC 7F52, and offered ECC RDIMM support with the large PCIe Gen4 footprint, it would impact the higher-end per-core frequency optimized segment for AMD. Our sense is that this chip was designed more like the lower-cost EPYCs rather than the higher-cost units to protect margins on the EPYC side. We did not have the Threadripper Pro 3945WX on hand, but this is likely more like the聽AMD EPYC 7272 Review 12 cores of Rome part in layout.

AMD Ryzen Threadripper Pro SKU StackAMD Ryzen Threadripper Pro SKU Stack

Overall we still get the large platform, but and higher clock speeds/ TDP, but the only significant feature we are missing is that this is 1 DIMM per channel versus 2 DIMMs per channel for the EPYC line and we also get a chipset to handle I/O such as USB connectivity.

With that background, let us get to benchmarks.



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