3. PCIe

2024-02-18 01:56| 来源: 网络整理| 查看: 265

3.2.1. DTS configuration¶

Generally, configure the power supply pin and reset pin in DTS according to the schematic diagram, and select the correct pcie controller node and PHY node to enable.

There is the following configuration about 4 x 2.5G mesh EXT board in kernel-5.10/arch/arm64/boot/dts/rockchip/roc-rk3588-rt-ext.dtsi:

/* pcie3.0 x 4 Lane */ &pcie30phy { rockchip,pcie30-phymode = ; status = "okay"; }; &pcie3x2 { num-lanes = ; reset-gpios = ; vpcie3v3-supply = ; rockchip,skip-scan-in-resume; rockchip,perst-inactive-ms = ; status = "okay"; }; &pcie3x4 { num-lanes = ; reset-gpios = ; vpcie3v3-supply = ; rockchip,skip-scan-in-resume; rockchip,perst-inactive-ms = ; status = "okay"; }; &vcc3v3_pcie30{ gpios = ; regulator-always-on; startup-delay-us = ; status = "okay"; };

pcie30phy：PHY node

pcie3x2：pcie3x2 controller node

pcie3x4：pcie3x4 controller node

reset-gpios：reset pin properties

vcc3v3_pcie30：power supply pin node

【本文地址】

公司简介

联系我们