The result of experiment indicates that the pipeline adder is faster others.

实验结果表明流水线加法器的速度高于其它结构实现的加法器。

It shows that mirrored adder is better than carry look ahead adder in arithmetic speed and layout.

结果表明镜像加法器在运算速度、版图布局上都优于超前进位加法器。

It is the hybrid of binary carry look-ahead adder of Brent-Kung~ and the carry select adder.

它结合了Brent-Kung对数超前进位加法器和进位选择加法器的优点，使得加法器的面积和连线减少了50%，而延时与加法器的长度的对数成正比。

Adder can be used to express a variety of values, such as: BCD, plus three yards, the major is based on a binary adder for computing.

加法器可以用来表示各种数值，如：BCD、加三码，主要的加法器是以二进制作运算。

Based on a new modified Wallace multiplier structure, named bi-forked Wallace multiplier structure, this paper presents the design of a highly re-configurable Multiplier for VLIW multimedia-processor. We found a reusable design method to extend multiplier with full adder array. The Structure can enable 32/16/8 bit operands, and has been optimized for speed and area.

在VLIW多媒体芯片的设计过程中，针对传统乘法器与加法器的不足，提出了一种新的分叉华莱氏树结构的乘法器模型，采用可重用的模块化设计思想，通过重用一位全加器阵列对乘法器进行扩展，处理器可以在一个乘法器单元内部同时支持多个32/16/8位的乘法运算，同时使乘法单元的速度和面积均得以优化。

As an example, in the design of a 4-bit ripple carry adder, the second and fourth full adders do not use output inverters for carry generation. one inverter delay is eliminated for every two full adders in the adder chain, and four transistors are reduced. Similarly, in complex designs like the multiplier, the output inverters for generating sum and carry can be used in alternative stages, thereby improving speed and reducing area.

例如，在4位行波进位加法器中，第2级和第4级的加法器不需要用输出反向器进行进位产生，因此，加法器链上的反向器延迟每两级全加器抵消一次，因此可以减少4个晶体管，类似的，在乘法器这样的复杂设计中，用于产生"和"以及"进位"的输出反向器可以用于其它方面，因此可以改善电路的速度和减小面积。

In practice, fast adders such as CLA adder is always used in the last stage of CSA array multiplier to increase its speed.

在实际电路中，为了提高乘法的速度，CSA（Carry-SaveAdder）阵列乘法器的最后一级常采用CLA加法器等快速加法器。

Wallace trees are the theoretically fastest multi operand adders, which can be used for obtaining the sum of partial products.

理论上 Wallace树结构加法器是乘法器中完成部分积求和的最快的多操作数加法器，但其互连复杂难于实现。

Signals of before and after NR decoding are entered to subtracter to obtain error signal, which is multiplied by imaginary part of the output of equalizer FIR so as to obtain output of discrimination phase.

本发明包括一个复均衡器的FIR、DFE、复乘器、加法器、NR解码器、减法器、实乘器、累加器、限幅器，它与均衡器结合，使解调后处理得到的复信号由I和Q路组成，经过复均衡FIR，输出仍为复信号，它与总相差φ复乘，进行相位解旋，之后取出实基带信号与DFE输出送入加法器得到均衡器输出，进入一个NR解码器后得到信号送入DFE作为输入，NR解码前后的信号进入减法器得到误差信号；它和均衡器FIR输出的虚部相乘得到鉴相输出，去噪声和限幅后进行相位解旋，去除相位偏差和相位抖动。

The principles of frequently used adders are presented, including the Ling type adder which has not been introduced in China.

其中介绍了常用的各种加法器的原理，包括目前国内尚未见提及的Ling型加法器，并给出了加法器中常用单元的电路形式。