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General Description The MAX9209/MAX9211/MAX9213/MAX9215 serialize 21 bits of LVTTL/LVCMOS parallel input data to three LVDS outputs. A parallel rate clock on a fourth LVDS output provides timing for deserialization. The MAX9209/MAX9211/MAX9213/MAX9215 feature programmable DC balance, which allows isolation between the serializer and deserializer using AC-cou- pling. The DC balance circuits on each channel code the data, limiting the imbalance of transmitted ones and zeros to a defined range. The companion MAX9210/ MAX9212/MAX9214/MAX9216 deserializers decode the data. When DC balance is not programmed, the serial- izers are compatible with non-DC-balanced, 21-bit seri- alizers like the DS90CR215 and DS90CR217. Two frequency ranges and two DC-balance default conditions are available for maximum replacement flexi- bility and compatibility with existing non-DC-balanced serializers. The MAX9209/MAX9211/MAX9213/MAX9215 are avail- |
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