cordic原理与FPGA实现（3）

2023-02-27 22:06| 来源: 网络整理| 查看: 265

cordic原理与FPGA实现（3）原创

mb6125f9b04a6f6 2022-08-15 16:22:06 博主文章分类：FPGA ©著作权

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一个Pipelined结构 16极流水线代码如下。但是有错误在pi/2相位整数倍点多了一个毛刺。还请各位指正谢谢

代码如下：

1: 1: 2: module cordic (clk,rst_n,ena,phase_in,sin_out,cos_out,eps); 3: 4: parameter DATA_WIDTH=16; 5: parameter PIPELINE=15; 6: input clk; 7: input rst_n; 8: input ena; 9: input [DATA_WIDTH-1:0] phase_in; 10: 11: output [DATA_WIDTH-1:0] sin_out; 12: output [DATA_WIDTH-1:0] cos_out; 13: output [DATA_WIDTH-1:0] eps; 14: 15: reg [DATA_WIDTH-1:0] sin_out; 16: reg [DATA_WIDTH-1:0] cos_out; 17: reg [DATA_WIDTH-1:0] eps; 18: 19: reg [DATA_WIDTH-1:0] phase_in_reg; 20: 21: reg [DATA_WIDTH-1:0] x0,y0,z0; 22: reg [DATA_WIDTH-1:0] x1,y1,z1; 23: reg [DATA_WIDTH-1:0] x2,y2,z2; 24: reg [DATA_WIDTH-1:0] x3,y3,z3; 25: reg [DATA_WIDTH-1:0] x4,y4,z4; 26: reg [DATA_WIDTH-1:0] x5,y5,z5; 27: reg [DATA_WIDTH-1:0] x6,y6,z6; 28: reg [DATA_WIDTH-1:0] x7,y7,z7; 29: reg [DATA_WIDTH-1:0] x8,y8,z8; 30: reg [DATA_WIDTH-1:0] x9,y9,z9; 31: reg [DATA_WIDTH-1:0] x10,y10,z10; 32: reg [DATA_WIDTH-1:0] x11,y11,z11; 33: reg [DATA_WIDTH-1:0] x12,y12,z12; 34: reg [DATA_WIDTH-1:0] x13,y13,z13; 35: reg [DATA_WIDTH-1:0] x14,y14,z14; 36: reg [DATA_WIDTH-1:0] x15,y15,z15; 37: 38: reg [1:0] quadrant[PIPELINE:0]; 39: 40: integer i; 41: 42: //get real quadrant and map to first_n quadrant 43: 44: always@(posedge clk or negedge rst_n) 45: begin 46: if(!rst_n) 47: phase_in_reg 赞收藏评论分享举报

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